The input offset voltages of complementary metal-oxide-semiconductor transistors (CMOS) have larger offset voltages than bipolar transistors for use in the input differential amplifier of comparators for analog-to-digital converters (ADC). For this reason, autozero-type inverters are often used as comparators in MOS ADC for correcting the undesirable large offset voltage.
The CMOS autozero-type inverter has a basic circuit as shown in FIG. 1(a). There are three switches SWr, SWi and SW1. SWr is connected to a reference voltage Vref; SWi is connected to an analog input voltage Vin; SW1 is a reset switch connected between the input terminal and the output terminal of an inverter INV. The operation is as follows:
1. During the autozero mode: SWr and SW1 are on, and SWi is off. The reference voltage Vref appears on the left side of a storage capacitor C, and a voltage V.sub.TH appears on the right-hand side of the capacitor as well as the input and output of the inverter, where V.sub.TH is the threshold voltage of the transfer characteristic of the inverter when the output voltage Vout is equal to the input voltage Vin as depicted by FIG. 1(b). This point lies in high-gain region of the inverter where the transfer characteristic is very steep. The voltage across the capacitor is equal to Vref-V.sub.TH. PA1 2. During the compare mode: SWi and SW1 are off, and SWr is on as shown in FIG. 2. The left-hand side of C is connected to an input voltage Vi. Since the voltage across a capacitor cannot change instantaneously, the voltage on the right-hand side of the capacitor becomes (Vi-Vref)+V.sub.TH. Due to the amplification of the inverter A, the output voltage Vo of the inverter becomes V.sub.TH -A(Vi-Vref). Thus Vi is compared with Vref and only the difference is amplified. Any fluctuation in V.sub.TH does not affect the amplification, and this double sampling correction technique is known as the "autozero" type.
Although the autozero type comparators for a parallel or "flash" ADC have the advantage of high-speed parallel operation, there are several drawbacks:
1. Since a large number of comparators are used for a high bit number ADC, the power dissipation and the chip size are very large.
2. Because of the large number of comparators, the loading of the input analog signal Vi is very heavy. The loading is a dynamic one in that the buffer for Vi experiences large loading variations during the switching transients which can cause serious Vi corruption.
Due to the foregoing drawbacks, it is more practical to use the sub-ranging (2-step) ADC. In the sub-ranging ADC, the input analog signal Vi is first converted into a digital signal with a coarse resolution during the first step, and then converted with a fine resolution in the second step. In so doing, each step need only to resolve one half of the number of total bits.
The basic principle of a sub-ranging N-bit ADC is shown in FIG. 3. After the more significant N/2 bits are converted in the first step by comparing with 2.sup.N/2 reference voltages, another set of 2.sup.N/2 reference voltages with a narrower voltage range of fine resolution centered around an analog voltage corresponding to the MSB in the first step are derived from a Reference Matrix. The result of the second step yields the less significant bit digital signals.
To perform the second step for fine resolution, the analog input signal Vi must be sampled and held (S/H), because the analog input signal must wait until the reference voltages have been derived from the Reference Matrix after the first coarse conversion step. The S/H circuit therefore plays an important role in a two-step sub-ranging ADC.
In a CMOS "autozero-type inverter" comparator for a sub-ranging ADC, the S/H function is commonly accomplished with a circuit as shown in FIGS.4(a) and (b), which is similar to FIG. 1(a) and also possesses the autozeo function. However, it should be noted that the input voltage Vi and the reference voltage Vref are now reversed during the autozero mode. The analog input voltage Vi appears at the left-hand side of the capacitor C, and the inverter threshold voltage V.sub.TH appears on the right-hand side of the capacitor. After the completion of the autozero operation, all the switches are off, and the capacitor can hold the potential difference Vi-V.sub.TH for the S/H function until the compare mode. During the compare mode, SWi is off, SWr is on and SW1 is off as shown in FIG. 4(b). During the compare mode for the more significant bits, Vref is a fixed reference voltage. During the compare mode for the less significant bits, Vref is derived from the digital signal of the more significant bits in the first step. Thus, this comparator can achieve the autozero function for both the first coarse conversion step for the more significant bits and the second fine conmversion step for the less significant bits. At the same time, this comparator performs the S/H function necessary for the subranging ADC.
For a sub-ranging ADC, this autozero technique is satisfactory when the operation has reached a steady-state. However, during dynamic operation, the Vi induces a spurious current CdVi/dt to flow through the capacitor C and the reset switch SW1 as shown in FIG. 5. Due to the ohmic resistance R.sub.sw1 of the reset switch, which is closed in the autozero mode, an offset voltage V=R.sub.sw1 CdVi/dt appears across SW1. This offset voltage adversely affects the accuracy of the autozero function of the inverter. The inaccuracy depends on the values of C and R.sub.sw1. At high input frequency of Vi, this RC time constant further limits the bandwidth of the ADC.